![]() ![]() I have about 100 IP cores that I have made which would need to be tested with 15.0, so its really not worth it. ![]() However the simulation is for part of a massive project which I do not want to have to upgrade to Quartus 15.0 - I feel it's too risky to do given how many times Altera seem to keep changing and breaking IP cores and messing around with how Qsys behaves. I understand that as of Quartus 15.0 (Altera ModelSim 10.3d), that Mixed-mode simulation is now supported. : Instantiation of '.' failed.# Time: 0 ps Iteration: 0 Instance. # ALTERA version supports only a single HDL# ** Fatal: (vsim-3039). As a result the simulation requires mixed mode simulation - the FIR filters generate VHDL simulation models, but the rest of my design is Verilog.įrom what I gather ModelSim Altera Starter Edition (v10.1d) does not support mixed mode simulation - I get the following error when simulating: I am currently using Quartus 14.0 and need to simulate a Stratix V Qsys design which uses FIR filters from the Altera FIR Filter Compiler as part of the design. ![]()
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